Method and device used for simulating CRT impulse type image display

ABSTRACT

Disclosed is a method and a device used for simulating CRT impulse type image display to overcome and improve the drawbacks and limitations of the hold type image display of the LCD display of the prior art, so as to eliminate the after image and the phenomenon of images overlapping outline blurring. To achieve the above mentioned purpose, a simulation device is provided, having a basic structure including a first input control line; a second input control line; a first input data line; a second input data line; a first capacitor; a second capacitor; a driving voltage output line; a first transistor comprising a first gate connected to a first input control line, a first source connected to a first input data line, and a first drain connected to a driving voltage output line, a first capacitor and the drain of the second transistor; and a second transistor comprising a second gate connected to a second input control line, a second source connected to a second input data line, and a second drain connected to a driving voltage output line, the drain of the first transistor and the second capacitor; wherein the first capacitor and the second capacitor connected to ground respectively, and the driving voltage output line is used to output the said simulation driving voltage to the said pixels of LCD panel for displaying images. It is characterized in that the said first and second input control lines are connected to a gate driver, and the said first and second data lines are connected to a data driver respectively. Also provided is a method used for simulating CRT impulse type image display.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and a device used for thesimulating CRT impulse type image display, and more particularly, to amethod and a device used for the simulating CRT impulse type imagedisplay with a liquid crystal display (LCD).

2. The Prior Arts

In recent years, the technology and device of liquid crystal display(LCD) have been very popular and widely used for the consumer electronicproducts, especially for video products, for example, television,computer, display, telephone handset, personal data assistant (PDA), andthe like. The varieties of the products are enormous, so as to stimulatethe tremendous rapid progress of the technology of liquid crystaldisplay and its direction of development is in agreement with therequirement of the future trend of development of electronic productstoward the features of light weight, thin thickness, short length, smallsize, low power consumption, and low heat dissipation, etc.

Presently, televisions and display devices made with the technology ofliquid crystal display have been produced in large quantities, toreplace the televisions and display devices made with the conventionalCRT. However, in the liquid crystal display technology of the presentdays, there still exist drawbacks and limitations, which must beovercome and improved.

With regard to the image display of CRT, it utilizes the “impulse type”image display. It produces light emissions by means of irradiating asingle electron beam on the pixels coated with fluorescence materials.However, as shown in curve (a) in FIG. 1, the pixel only produces theemission of light in an instant of a minute portion of time in eachframe period. Therefore, it seems almost no visional overlappingphenomenon will be noticed for the images displayed between the frames.

However, for the LCD image display, it utilizes the “hold type” imagedisplay due to the intrinsic property of the LCD material. It producesthe image display through the optical response (namely, the gray levelresponse) by means of applying driving voltages on the LCD material.Nevertheless, due to the limitation of the intrinsic property of theliquid crystal material, the image it displays occupies the predominantportion of time of that frame as shown in curve (c) in FIG. 1. And forevery time its image changes, its luminance (or brightness) also changesstepwise. Therefore, from the viewpoint of the spectators, he may feelthe overlapping of the image of the new frame on that of the old frame,so as to cause the blurring of the image outlines and produce thephenomenon of the so-called “after-image”.

When utilizing LCD display as the displaying device of personalcomputer, this after image phenomenon is not evident and usually willnot be noticed, since the images it displays are static display for mostof the time. However, when utilizing this LCD displaying device astelevision, the problem of slow LCD gray scale optical response will bemore pronounced, since almost all the television programs utilizedynamic image displays. Therefore, the image displaying effectiveness ofthe conventional LCD television is evidently inferior to that of CRTtelevision.

In order to eliminate the above-mentioned after image caused by the LCDdisplay device slow optical response, and the resulting image outlineblurring phenomenon, currently most LCD television manufacturers try toconvert the “hold type” image display of the LCD displaying device intothe simulated (or pseudo) impulse type LCD displaying device similar tothat of the CRT displaying device, by means of a kind of the so-called“overdrive” technology, with its image only occupies a portion of theframe period according to the optical response as shown in curve (b) inFIG. 1, namely, the image is not displayed during a portion of eachframe period.

The kind of method utilized in this technology is a kind of “overdrive”method. It applies to the liquid crystal material the voltage (forexample code 200) which is much higher than the originally set targetvoltage (for example code 120), so as to expedite and accelerate theresponse speed of the liquid crystal molecules, and accelerating them toreach the predetermined optical response value, and as such shorteningthe liquid crystal gray level response time to less than one frameperiod, as shown in curve (b) in FIG. 1.

However, even the LCD display device made with this kind of over drivetechnology is able to shorten its gray level response time to less thanand within one frame period, yet due to the intrinsic property of theliquid crystal, the generation of the optical response is slow so is itsdecline. Therefore, the image overlapping and the image outlinesblurring phenomenon of the “after image” for the images displayed stillcan not be eliminated completely

In order to completely eliminate the “after image”, presently there arethree methods adopted by the prior art, which are listed as follows:

-   -   (1) to write black data or black images into the frame in the        remaining portion of that frame period after the original formal        image is displayed;    -   (2) to shut off the backlight, for example, the blink light        method as announced by Hitachi;    -   (3) the combination of the above methods (1) and (2), namely,        both write in black image and shut off the backlight.

And in the following we will explain their respective drawbacks andlimitations in detail.

First, referring to FIGS. 2A-2C, which indicate the methods adopting bythe prior art in simulating the CRT impulse type image display with LCDdisplay device, the images displayed by the liquid crystal display ofthe prior art are composed of a series of frames 1, 2, 3, and 4. Themethod utilized is to insert the complete black frames 11, 12, and 13between frames 1, 2; frames 2, 3; and frames 3, 4 so as to achieve thepurpose of simulating CRT impulse type image display, and at the sametime the backlight source at time points 14-20 corresponding to the timepoints of the above-mentioned frames are all in the illumination state.

Next, we are going to explain the second method of the prior art. Pleaserefer to FIG. 2B. At this time the images displayed by the LCD displayconsist of the sequentially displayed frames 1-7. The second method isperformed by shutting off the backlight source at time points 22, 24,and 26 corresponding to the time points of frames 2, 4, and 6 and thebacklight source at time points 21, 23, 25, and 27 corresponding to timepoints of frames 1, 3, 5, 7, and 9 are in the illumination state and inthis manner, achieving the purpose of simulating CRT display impulsetype image display with LCD display and eliminating the “after image”.

And then next, we are going to explain the third method of the priorart. Please refer to FIG. 2C, which indicates that the images displayedby the LCD display are composed of a series of sequentially displayedframes 1-4. The method is carried out by inserting the complete blackframes 11, 12, and 13 between frames 1, 2; frames 2, 3; and frames 3, 4respectively, and by putting the backlight source at time points 22, 24,and 26 corresponding to those of frames 11, 12, and 13 into the shut-offstate, and by putting the backlight source at other time pointscorresponding to those of frames 1, 2, 3, and 4 into the illuminationstate. And that is to say, the third method achieves the effect ofsimulating CRT display impulse type image display with LCD display byinserting the complete black frames between frames 1, 2, 3, and 4, andat the same time utilizing this blink light mode of alternateillumination state and shut off state by means of shutting off thebacklight source at the corresponding time points.

However, the three above-mentioned methods have their respectivedrawbacks and limitations.

First, the first method of inserting complete black frames betweenframes necessitates the addition of extra equipments, for example,frequency doubling device. Supposing that the original image displayingspeed is 60 frames/min, then the application of this method necessitatesthe addition of the frequency doubling device to increase the imagedisplaying speed to 120 frames/min, and wherein half of the number areused for inserting those black frames. Therefore, the utilization ofthis method would increase the cost of the equipment. Besides, thedoubling of the image display frequency leads to the increase ofelectric-magnetic interference (EMI), and these are the drawbacks andlimitations of the first method the prior art.

Next, the application of the second method also necessitates theaddition of frequency doubling device, so as to achieve the equivalentnumber of display frames/unit time. Since half of the frames displayedin the unit time correspond to the backlight shut-off state and cannotbe displayed as visible images. Therefore, the second method willincrease the cost of the equipment, and it will also cause the increaseof EMI. In addition, it requires the addition of extra equipment so asto make the backlight source blink, and therefore it further increasesthe cost of this method. And these are the drawbacks and limitations ofthe second method of the prior art.

And next, the third method of the prior art is the combination of theabove two methods, namely, inserting the black frames and blinking thebacklight modules. As such the drawbacks and limitations of the thirdmethod includes those of the above two methods. Therefore, it is notsatisfying either.

In addition, in the above first and second methods, since thecharacteristics and speeds of optical response of different liquidcrystal materials are different, the method of inserting black frames isnot suitable for certain liquid crystal materials. Because for certainliquid crystal materials, their optical responses are fast frombrightness to dark, and are slow from dark to brightness; but for otherliquid crystal materials their optical responses are slow frombrightness to dark, and are fast from dark to brightness. Therefore, theeffectiveness of inserting black frames at equal time intervals insimulating CRT impulse type image display is not ideal and thus notsatisfying, and in certain circumstances it is even not suitable forapplication. And it cannot achieve the purpose of simulating CRT displaywith LCD display, and it is not able to achieve the effectiveness ofeliminating the “after image” either.

In view of the various above mentioned drawbacks and limitations of theprior art, the inventor of the present case dedicates all his talent,ingenuity, knowledge and experience in this field to the relatedresearch, development, experiment, and improvement, so as to bring aboutthe realization of the present invention.

SUMMARY OF THE INVENTION

Therefore, the purpose of the present invention is to provide a deviceused for simulating CRT impulse type image display so as to overcome andimprove the drawbacks and limitations of the related prior art. Itneither utilizes the method of inserting black frames, nor does itutilize the method and design of blinking the backlights. Instead, itmakes use of the method of providing the scanning black lines on thescreen of the LCD display, to ensure achieving the purpose of simulatingCRT impulse type image display, and to effectively eliminate the “afterimage” and phenomenon of image outline blurring, so as to significantlyimprove the quality of the displayed images of the LCD display, and savethe spending on the additional equipment.

In order to achieve the above mentioned purpose, the present inventionprovides a device to achieve simulating CRT display with LCD display,and it basic structure comprising:

A first input control line; a second input control line; a first inputdata line; a second input data line; a first capacitor; a secondcapacitor; a driving voltage output line; a first transistor, comprisinga first gate connected to a first input control line, a first sourceconnected to a first input data line, and a first drain connected to adriving voltage output line, a first capacitor and the drain of thesecond transistor; and a second transistor, comprising a second gateconnected to a second input control line, a second source connected to asecond input data line, and a second drain connected to a drivingvoltage output line, the drain of the first transistor and the secondcapacitor; wherein the first capacitor and the second capacitorconnected to ground respectively, and the driving voltage output line isused to output the said simulation driving voltage to the said pixels ofLCD panel for displaying images; and it is characterized in that, thesaid first and second input control lines are connected to a gatedriver, and the said first and second data lines are connected to a datadriver respectively.

In the following we will explain in detail the embodiments and othervariations of the device of the present invention used for simulatingCRT impulse type image display.

The present invention also provides a method used for simulating CRTimpulse type image display.

The various features and advantages of the present invention can be morethoroughly understood through the detailed description of the followingembodiments with reference to the attached drawings, wherein similarreference numbers are used for similar elements.

BRIEF DESCRIPTION OF THE DRAWINGS

The related drawings in connection with the detailed description of thepresent invention to be made later are described briefly as follows, inwhich:

FIG. 1 is the diagram of comparison of optical response curves of CRTimage display, liquid crystal image display, and the simulated CRTimpulse type image display;

FIGS. 2(a) to 2(c) indicate the methods of inserting black frames, blacklight blinking, and the combination of the two used by the prior art insimulating CRT display with LCD display;

FIG. 3(a) is the schematic diagram indicating the pixel array formed bythe cross points of a plurality of gate lines and data lines, and thedriving circuit formed by a plurality of data driver and gate driveraccording the first embodiment of the present invention;

FIG. 3(b) indicates the simulation device according to the firstembodiment of the present invention;

FIGS. 4(a) to 4(e) are the corresponding waveform diagrams of thecontrol voltage pulse, driving voltage pulse, and the liquid crystaloptical response curve generated by the simulation device according tothe first embodiment of the present invention;

FIG. 5(a) is the schematic diagram indicating the pixel array formed bythe cross points of a plurality of gate lines and data lines, and thedriving circuit formed by a plurality of data driver and gate driveraccording the second embodiment of the present invention;

FIG. 5(b) indicates the simulation device according to the secondembodiment of the present invention;

FIGS. 6(a) to 6(g) are the corresponding waveform diagrams of thecontrol voltage pulse, driving voltage pulse, and the liquid crystaloptical response curve generated by the simulation device according tothe second embodiment of the present invention;

FIG. 7(a) is the schematic diagram indicating the pixel array formed bythe cross points of a plurality of gate lines and data lines, and thedriving circuit formed by a plurality of data driver and gate driveraccording the third embodiment of the present invention;

FIG. 7(b) indicates the simulation device according to the thirdembodiment of the present invention;

FIGS. 8(a) to 8(d) are the corresponding waveform diagrams of thecontrol voltage pulse, driving voltage pulse, and the liquid crystaloptical response curve generated by the simulation device according tothe third embodiment of the present invention;

FIG. 9(a) is the schematic diagram indicating the pixel array formed bythe cross points of a plurality of gate lines and data lines, and thedriving circuit formed by a plurality of data driver and gate driveraccording the fourth embodiment of the present invention;

FIG. 9(b) indicates the simulation device according to the fourthembodiment of the present invention;

FIGS. 10(a) to 10(d) are the corresponding waveform diagrams of thecontrol voltage pulse, driving voltage pulse, and the liquid crystaloptical response curve generated by the simulation device according tothe fourth embodiment of the present invention;

FIG. 11(a) is the schematic diagram indicating the pixel array formed bythe cross points of a plurality of gate lines and data lines, and thedriving circuit formed by a plurality of data driver and gate driveraccording the fifth and sixth embodiments of the present invention;

FIG. 11(b) indicates the simulation device according to the fifth andthe sixth embodiments of the present invention;

FIGS. 12(a) to 12(e) are the corresponding waveform diagrams of thecontrol voltage pulse, driving voltage pulse, and the liquid crystaloptical response curve generated by the simulation device according tothe fifth embodiment of the present invention;

FIGS. 13(a) to 13(e) are the corresponding waveform diagrams of thecontrol voltage pulse, driving voltage pulse, and the liquid crystaloptical response curve generated by the simulation device according tothe six embodiment of the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following the embodiments of the present invention will bedescribed with reference to the attached drawings. And similar referencenumbers represent similar elements.

In the following embodiments, the waveforms displayed are mainly used asinstruments or tools to describe the voltage applied on the liquidcrystal, and the characteristics and behaviors of the liquid crystaloptical response. And the features and advantages of the presentinvention will be explained based on the above descriptions.

In FIGS. 4, 6, 8, 10, and 12 in the following five embodiments, theabscissa indicates time, and its units is millisecond (ms), with A1 toA6 as the sequentially progressing time points; and its ordinateindicates driving voltage, with “code” as its displaying unit. For thesake of convenient explanation, in the above-mentioned drawings, thetime of the waveform progression on the abscissa can be divided into(N−1)th, Nth, (N+1)th , (N+2)th, and so on, equal frame time partitionsas units of frame time. And the dotted lines in FIGS. 4(a), 6(a), 8(a),10(a), and 12(a) indicate the optical response (namely, the gray levelresponse) path characteristic curves for the liquid crystal moleculesunder the application of various different driving voltages. Usually,the optical response is the luminance displayed by the liquid crystal,and with nits (cd/m²) as its unit.

In the following descriptions the meanings of the symbols represented bythe pulse of voltage in FIGS. 4(a) to 4(e), 6(a) to 6(g), 8(a) to 8(d),10(a) to 10(d), and 12(a) to 12(e) can be better understood byreferencing the circuit structure of FIGS. 3(b), 5(b), 7(b), 9(b), and11(b). For example, the waveform shown in FIG. 4(b) represents the pulseof control voltage applied on the gate of transistor Q of the simulationdevice in FIG. 3(b); the waveform shown in FIG. 4(c) represents thepulse of control voltage applied on the gate of transistor Q′ of thesimulation device in FIG. 3(b); the waveform shown in FIG. 4(d)represents the pulse of driving voltage applied on the source oftransistor Q of the simulation device in FIG. 3(b); the waveform shownin FIG. 4(e) represents the pulse of driving voltage applied on thesource of transistor Q′ of the simulation device in FIG. 3(b); V_(LC)represents the pulse of output driving voltage generated by thesimulation device, and V_(COM) represents the reference voltage, Theabscissa representing time is arranged below FIG. 4(e) for jointly usedby FIGS. 4(a) to 4(e), and for being conveniently referenced andcompared between FIGS. 4(a) to 4(e); and A1 to A6 represent thesequentially progressing points of time. And the similar details of theremaining FIGS. 6, 8, 10, and 12 can be explained similarly as above.

The CRT simulation method and device of the present invention will beexplained in the following with the circuit diagram, the control voltagepulse waveform of the LCD display pixel unit, waveform of the drivingvoltage pulse, and the liquid crystal optical response characteristiccurve of the respective five embodiments

Embodiment 1

In the following analysis, please refer to FIGS. 3(a), 3(b) and FIGS.4(a) to 4(e) as we explain first embodiment of the present invention.

First, please refer to FIG. 3(a), which indicates: the pixel arrayformed by the cross points of a plurality of gate lines and data lines,and the driving circuit formed by a plurality of data driver and gatedriver according to the first embodiment of the present invention. AndFIG. 3(b) represents the simulation device according to the firstembodiment.

Simulation Device

According to FIGS. 3(a) and 3(b) the simulation device comprises: afirst input control line (G₁); a second input control line (G_(1′)); afirst input data line (D₁); a second input data line (D_(1′)); a firstcapacitor (C_(S)); a second capacitor (C_(LS)); driving voltage outputline; a first transistor (Q) comprising a first gate connected to thefirst input control line (G₁), a first source connected to the firstinput data line (D₁), and a first drain connected to the driving voltageoutput line and the first capacitor (C_(S)) and the drain of the secondtransistor (Q′); and a second transistor (Q′) comprising a second gateconnected to the second input control line (G_(1′)), a second sourceconnected to the second input data line (D_(1′)), a second drainconnected to the drain of the said first transistor and the secondcapacitor (C_(LC)) and driving voltage output line; wherein the saidfirst capacitor and the said second capacitor are storage capacitor andliquid crystal equivalent capacitor respectively and are connected toground, and the driving voltage output line is used to output thedriving voltage used for simulation to the said pixels of the LCD panelso as to display images, and it is characterized in that, the said firstand second input control lines are connected to a gate driver, and thesaid first and second input data lines are connected to a data driverrespectively.

Simulation Method

The following is the simulation method used for the simulation deviceaccording to the first embodiment of the present invention, comprisingthe following steps: (I) providing the first control signal (G₁) withperiodic pulse waveforms to the first gate of the first transistor (Q)of the said circuit; (II) providing the second control signal (G_(1′))with periodic pulse waveforms to the second gate of the secondtransistor (Q′) of the said circuit, wherein the second control signal(G_(1′)) is the same as the first control signal (G₁) except the phasedelay; (III) providing the first data signal (D₁) to the source of thefirst transistor (Q) of the said circuit, when activated by the saidfirst control signal (G₁), the said circuit feeds the first data signal(D₁) to the said driving voltage output line; (IV) providing the seconddata signal (D_(1′)) to the source of the second transistor (Q′) of thesaid circuit, when activated by the said second control signal (G_(1′)),the said circuit feeds the second data signal (D_(1′)) to the saiddriving voltage output line; and (V) outputting the said output drivingvoltages generated by the above steps to the said pixels, so as todisplay images.

Waveform Analysis

In the following analysis, please refer to FIGS. 4(a) to 4(e) as wedescribe in detail the relations between the waveforms of the pulses ofcontrol voltages G₁, G_(1′) and the pulses of the driving voltages D₁,D_(1′), V_(LC) generated by the simulation device of FIGS. 3(a) and 3(b)according the first embodiment of the present invention.

When the pulse of the control voltage of the simulation device is G₁(FIG. 4(b)), then the pulse of its corresponding driving voltage is D₁(FIG. 4(d)). When the pulse of the control voltage of the device is G₁(FIG. 4(c)), then the pulse of its corresponding driving voltage is D₁,(FIG. 4(e)). And pulse of the actual combined output driving voltagegenerated by the simulation device of the present invention to theliquid crystal is V_(LC) (FIG. 4(a)).

In the following discussion, the driving voltages V₁, V₂, V₃ can beconsidered as a kind of voltage value expressed in “code”.

It must be re-emphasized here that the said driving voltage can 6reachits target voltage momentarily, however, the liquid crystal moleculeshave to take a certain period of response time to reach its opticalresponse target position after being applied the driving voltages. Thisis due to the intrinsic property of the liquid crystal.

Since usually AC voltage is utilized as the voltage for driving theliquid crystal, therefore, this voltage indicates the phenomenon ofalternating positive and negative phases during the control and drivingprocess of the liquid crystal (namely, the waveforms of the pulses ofdriving voltages D₁, D_(1′); and V_(LC) indicate the phenomenon ofalternating positive and negative phases relative to the referencevoltage V_(COM)).

These waveforms proceed sequentially and periodically from time pointsA1 to A6 repeatedly in the following manner:

The value of driving voltage pulse D_(1′) in the (N−1)th frame beforetime point A1 is V_(1′) (code 0), and the value of the driving voltagepulse V_(LC) is V_(1′) (code 0) of negative polarity; at time point A1,the waveform enters the Nth frame, at this time the value of the drivingvoltage pulse D₁ increases to V2 (code 32), and due to the activation ofthe control voltage pulse G₁, therefore the value of driving voltagepulse V_(LC) generated by the simulation device also increases to V₂(code 32) of positive polarity and remains so until time point A2; thenthe time proceeds to time point A2, at this time the value of drivingvoltage pulse D_(1′) is V₁ (code 0), and due to the activation ofcontrol voltage pulse G_(1′), resulting in the value of driving voltagepulse V_(LC) to drop momentarily from V₂ (code 32) to V₁ (code 0) and isstill of positive polarity, and this value is maintained until timepoint A3; then the time proceeds to time point A3 and enters the (N+1)thframe, at this time the value of the driving voltage pulse D₁ drops toV_(3′) (code 120) and is of negative polarity, and due to the activationof control voltage pulse G₁, the value of the driving voltage pulseV_(LC) also momentarily drops to V_(3′) (code 120) of negative polarity,and it remains so until time point A4; then time proceeds to A4, at thistime, the value of driving voltage pulse D_(1′) is still V_(1′) (code0), and due to the activation of control voltage pulse G_(1′), resultingin the value of the driving voltage pulse V_(LC) also increases toV_(1′) (code 0) and is still of negative polarity and it remains sountil time point A5; then time proceeds to time point A5 and starts toenter the (N+2)th frame, at this time the value of the driving voltagepulse D₁ increases to V₃ (code 120), and due to the activation of thecontrol voltage pulse G₁, resulting in the value of the driving voltagepulse V_(LC) also increases momentarily to V₃ (code 120) of positivepolarity, and it remains so until time point A6.

The variations of control voltage pulses G₁, G_(1′) and driving voltagepulses D₁, D₁, and V_(LC) at the various time points after time pointsA6 can easily be inferred based on the above descriptions.

The dotted line as shown in FIG. 4(a) is the liquid crystal opticalresponse characteristic curve produced while performing the simulationdrive. When the output driving voltage of the simulation device betweeneach time point is code 0 as shown in the figure, this means that theblack line scanning is performed on the display screen during thisperiod, and by doing so, it can achieve the same results as insertingblack frames or shutting off the backlights, so as to achieve thepurpose of simulating CRT display impulse type image display.

In addition, the n shown at pulse G_(1′) in the Nth frame as shown inFIG. 4(c) indicates n pulses, which means that there exists the timedifference of n scanning lines between the control voltage pulse G₁ andG_(1′) in the same frame, namely, from the standpoint of the pixel,another control driving pulse G₁ will be input, at only nG₁ pulses afterthe first G₁ pulse. And this interval of time represented by n can beproperly adjusted by the designer depending on the actual requirementssuch as the property of liquid crystal material etc., so as to ensureachieving the effectiveness of simulating CRT display impulse type imagedisplay. And this is the most important advantage of the presentinvention over prior art.

Embodiment 2

In the following analyses, please refer to FIGS. 5(a), 5(b) and FIGS.6(a) to 6(g) as we explain second embodiment of the present invention.

First, please refer to FIG. 5(a), which indicates: the pixel arrayformed by the cross points of a plurality of gate lines and data lines,and the driving circuit formed by a plurality of data driver and gatedriver according to the second embodiment of the present invention. AndFIG. 5(b) represents the simulation device according to the secondembodiment.

Simulation Device

According to FIGS. 5(a) and 5(b) the simulation device of the secondembodiment comprises: a first input control line (G₁); a second inputcontrol line (G_(1′)); a first input data line (D₁); a second input dataline (D_(1′)); a third input data line (D′); a fourth input data line(D); a fifth input data line (Ds); a first capacitor (C_(S)); a secondcapacitor (C_(LS)); a third transistor (Q3); a fourth transistor (Q4);driving voltage output line; a first transistor (Q) comprising a firstgate connected to the first input control line (G₁), a first sourceconnected to the input data line (D₁), and a first drain connected tothe driving voltage output line and the first capacitor (Cs) and thedrain of the second transistor (Q′); and a second transistor (Q′)comprising a second gate connected to the second input control line(G_(1′)), a second source connected to the second input data line(D_(1′)), a second drain connected to the drain of the said firsttransistor and the second capacitor (C_(LC)) and driving voltage outputline; wherein the said first capacitor and the said second capacitor arestorage capacitor and liquid crystal equivalent capacitor respectivelyand are connected to ground, and the driving voltage output line is usedto output the driving voltage used for simulation to the said pixels ofthe LCD panel so as to display images, and it is characterized in thatthe said first and second input control lines are connected to a gatedriver, and the said first and second input data lines are connected tothe drains of two another switching transistors (Q3, Q4) connected inparallel, the sources of the said two switching transistors connected inparallel are connected to a data driver, with its gate connected to thethird and fourth input data lines (D′, D); and the time differencebetween the periodic pulse waveforms of the said first and secondcontrol signals (G1, G1′) is the time difference across n scanning linesgenerated by n pulses, and which can be adjusted.

Simulation Method

The following is the simulation method used for the simulation deviceaccording to the second embodiment of the present invention, comprisingthe following steps: (I) providing the first control signal (G₁) withperiodic pulse waveforms to the first gate of the first transistor (Q)of the said circuit; (II) providing the second control signal (G_(1′))with periodic pulse waveforms to the second gate of the secondtransistor (Q′) of the said circuit wherein the second control signal(G_(1′)) is the same as the first control signal (G₁) except the phasedelay; (III) providing the fifth data signal (Ds) to the sources of thethird transistor (Q3) and fourth transistor (Q4) connected in parallel;(IV) providing the third data signal (D′) to the gate of the thirdtransistor (Q3); (V) providing the voltage pulse generated by the drainof the third transistor to the source of the first transistor (Q1) asthe first data signal (D1), when the said first transistor (Q1) isactivated by the first control signal (G1), the first data signal (D1)is fed by the said circuit to the driving voltage output line; (VI)providing the fourth data signal (D) to the gate of the fourthtransistor (Q4); (VII) providing the voltage pulse generated by thedrain of the fourth transistor to the source of the second transistor(Q′) as the second data signal (D1′), when the said second transistor(Q′) is activated by the second control signal (G1′), the second datasignal (D1′) is fed by the said circuit to the driving voltage outputline; and (VIII) outputting the said output driving voltage generated bythe above steps to the said pixels so as to display images.

Waveform Analysis

In the following analysis, please refer to FIGS. 6(a) to 6(g) as wedescribe in detail the relations between the waveforms of the pulses ofcontrol voltages G₁, G_(1′) and the pulses of the driving voltages D₁,D_(1′), V_(LC) generated by the simulation device of FIGS. 5(a) and 5(b)according the second embodiment of the present invention.

Since usually AC voltage is utilized as the voltage for driving theliquid crystal, therefore, this voltage indicates the phenomenon ofalternating positive and negative phases during the control and drivingprocess of the liquid crystal (namely, the waveforms of the pulses ofdriving voltages D₁, D_(1′), and V_(LC) indicate the phenomenon ofalternating positive and negative phases relative to the referencevoltage V_(COM)).

These waveforms proceed sequentially and periodically from time pointsA1 to A6 repeatedly in the following manner:

The value of driving voltage pulse D_(1′) in the (N−1)th frame beforetime point A1 is V_(1′) (code 0), and the value of the driving voltagepulse V_(LC) is V_(1′) (code 0) of negative polarity; at time point A1,the waveform enters the Nth frame, at this time the value of the drivingvoltage pulse D₁ increases to V2 (code 32), and due to the activation ofthe control voltage pulse G₁, therefore the value of driving voltagepulse V_(LC) generated by the simulation device also increases to V₂(code 32) of positive polarity and remains so until time point A2; thenthe time proceeds to time point A2, at this time the value of drivingvoltage pulse D_(1′) is V₁ (code 0), and due to the activation ofcontrol voltage pulse G_(1′), resulting in the value of driving voltagepulse V_(LC) to drop momentarily from V₂ (code 32) to V₁ (code 0) and isstill of positive polarity, and this value is maintained until timepoint A3; then the time proceeds to time point A3 and enters the (N+1)thframe, at this time the value of the driving voltage pulse D₁ drops toV_(3′) (code 120) and is of negative polarity, and due to the activationof control voltage pulse G₁, the value of the driving voltage pulseV_(LC) also momentarily drops to V₃′ (code 120) of negative polarity,and it remains so until time point A4; then time proceeds to A4, at thistime, the value of driving voltage pulse D_(1′) is still V_(1′) (code0), and due to the activation of control voltage pulse G_(1′), resultingin the value of the driving voltage pulse V_(LC) also increases toV_(1′) (code 0) and is still of negative polarity and it remains sountil time point A5; then time proceeds to time point A5 and starts toenter the (N+2)th frame, at this time the value of the driving voltagepulse D₁ increases to V₃ (code 120), and due to the activation of thecontrol voltage pulse G₁, resulting in the value of the driving voltagepulse V_(LC) also increases momentarily to V₃ (code 120) of positivepolarity, and it remains so until time point A6.

The variations of control voltage pulses G₁, G_(1′) and driving voltagepulses D₁, D_(1′), and V_(LC) at the various time points after timepoints A6 can easily be inferred based on the above descriptions.

FIGS. 6(d) and 6(e) indicate the waveforms of the voltage pulses of thethird and fourth data signals of FIG. 5(a).

The dotted line as shown in FIG. 6(a) is the liquid crystal opticalresponse characteristic curve produced while performing the simulationdrive. When the output driving voltage of the simulation device betweeneach time point is code 0 as shown in the figure, this means that theblack line scanning is performed on the display screen during thisperiod, and by doing so, it can achieve the same results as insertingblack frames or shutting off the backlights, so as to achieve thepurpose of simulating CRT display impulse type image display.

In addition, the n shown at pulse G_(1′) in the Nth frame as shown inFIG. 6(c) indicates n pulses, which means that there exists the timedifference of n scanning lines between the control voltage pulse G₁ andG_(1′) in the same frame, namely, from the standpoint of the pixel,another control driving pulse G₁ will be input, at only nG₁ pulses afterthe first G₁ pulse. And this interval of time represented by n can beproperly adjusted by the designer depending on the actual requirementssuch as the property of liquid crystal material etc., so as to ensureachieving the effectiveness of simulating CRT display impulse type imagedisplay. And this is the most important advantage of the presentinvention over prior art.

For the sake of easy and convenient explanation and understanding, thewaveform of the driving voltage pulse V_(LC) output by the simulationdevice of the present Embodiment as shown above is the same as that ofEmbodiment 1, so as to avoid it being too complicated to understand inthe process of explanation. However, the waveform can be designed tohave various variations according to the actual requirements of the LCDdisplay.

Embodiment 3

In the following analyses, please refer to FIGS. 7(a), 7(b) and FIGS.8(a) to 8(d) as we explain third embodiment of the present invention.

First, please refer to FIG. 7(a), which indicates: the pixel arrayformed by the cross points of a plurality of gate lines and data lines,and the driving circuit formed by a plurality of data driver and gatedriver according to the third embodiment of the present invention. AndFIG. 7(b) represents the simulation device according to the thirdembodiment.

Simulation Device

According to FIGS. 7(a) and 7(b) the simulation device comprises: afirst input control line (G₁); a second input control line (G_(1′)); afirst input data line (D₁); a first capacitor (Cs); a second capacitor(C_(LS)); driving voltage output line; a first transistor (Q) comprisinga first gate connected to the first input control line (G₁), a firstsource connected to the first input data line (D₁), and a first drainconnected to the driving voltage output line and the first capacitor(Cs) and the second drain of the second transistor (Q′); and a secondtransistor (Q′) comprising a second gate connected to the second inputcontrol line (G_(1′)), a second source connected to ground, a seconddrain connected to the drain of the said first transistor and the secondcapacitor (C_(LC)) and driving voltage output line; wherein the saidfirst capacitor and the said second capacitor are storage capacitor andliquid crystal equivalent capacitor respectively and are connected toground, and the driving voltage output line is used to output thedriving voltage used for simulation to the said pixels of the LCD panelso as to display images, and it is characterized in that the said firstand second input control lines are connected to a gate driver, and thesaid first input data line is connected to a data driver; and the timedifference between the waveforms of the periodic pulses of the first andsecond control signals is the time difference across n scanning linesgenerated by n pulses, and which can be adjusted.

Simulation Method

The following is the simulation method used for the simulation deviceaccording to the third embodiment of the present invention, comprisingthe following steps: (I) providing the first control signal (G₁) withperiodic pulse waveforms to the first gate of the first transistor (Q)of the said circuit; (II) providing the second control signal (G_(1′))with periodic pulse waveforms to the second gate of the secondtransistor (Q′) of the said circuit, wherein the second control signal(G_(1′)) is the same as the first control signal (G₁) except the phasedelay; (III) providing the first data signal (D₁) to the source of thefirst transistor (Q) of the said circuit, when activated by the saidfirst control signal (G₁), the said circuit feeds the first data signal(D₁) to the said driving voltage output line; (IV) when activated by thesecond control signal (G_(1′)), the ground potential voltage (code 0) isfed by the said circuit to the driving voltage output line; and (V)outputting the said output driving voltages generated by the above stepsto the said pixels so as to display images.

Waveform Analysis

In the following analysis, please refer to FIGS. 8(a) to 8(d), as wedescribe in detail the relations between the waveforms of the pulses ofcontrol voltages G₁, G_(1′) and the pulses of the driving voltages D₁,D_(1′), V_(LC) generated by the simulation device of FIGS. 7(a) and 7(b)according the third embodiment of the present invention.

Since usually AC voltage is utilized as the voltage for driving theliquid crystal, this voltage indicates the phenomenon of alternatingpositive and negative phases during the control and driving process ofthe liquid crystal (namely, the waveforms of the pulses of drivingvoltages D₁, D_(1′) and V_(LC) indicate the phenomenon of alternatingpositive and negative phases relative to the reference voltage V_(COM)).

These waveforms proceed sequentially and periodically from time pointsA1 to A6 repeatedly in the following manner:

The value of driving voltage pulse D₁ in the (N−1)th frame before timepoint A1 is V_(2′) (code 32), and the value of the driving voltage pulseV_(LC) is V_(com) (since the source of the second transistor isconnected to V_(com)); at time point A1, the waveform enters the Nthframe, at this time the value of the driving voltage pulse D₁ increasesto V2 (code 32), and due to the activation of the control voltage pulseG₁, therefore the value of driving voltage pulse V_(LC) generated by thesimulation device also increases to V₂ (code 32) of positive polarityand it remains so until time point A2; then the time proceeds to timepoint A2, at this time the value of driving voltage pulse D₁ is still V₂(code 32), and due to the activation of control voltage pulse G_(1′)(since the source of the second transistor is connected to V_(com)),resulting in the value of driving voltage pulse V_(LC) to dropmomentarily from V₂ (code 32) to V₁ (code 0) and is still of positivepolarity, and this value is maintained until time point A3; then thetime proceeds to time point A3 and enters the (N+1)th frame, at thistime the value of the driving voltage pulse D₁ drops to V₃′ (code 120)and is of negative polarity, and due to the activation of controlvoltage pulse G₁, the value of the driving voltage pulse V_(LC) alsomomentarily drops to V_(3′) (code 120) of negative polarity, and itremains so until time point A4; then time proceeds to time point A4, atthis time, the value of driving voltage pulse D₁ is still V_(3′) (code120) of negative polarity, and due to the activation of control voltagepulse G_(1′) (since the source of the second transistor is connected toV_(com)), resulting in the value of the driving voltage pulse V_(LC)also increases to V_(com) (code 0) and is still of negative polarity andit remains so until time point A5; then time proceeds to time point A5and starts to enter the (N+2)th frame, at this time the value of thedriving voltage pulse D₁ increases to V₃ (code 120), and due to theactivation of the control voltage pulse G₁, resulting in the value ofthe driving voltage pulse V_(LC) also increases momentarily to V₃ (code120) of positive polarity, and it remains so until time point A6.

The variations of control voltage pulses G₁, G_(1′) and driving voltagepulses D₁, D_(1′) and V_(LC) at the various time points after timepoints A6 can easily be inferred based on the above descriptions.

The dotted line as shown in FIG. 8(a) is the liquid crystal opticalresponse characteristic curve produced while performing the simulationdrive. When the output driving voltage V_(LC) of the simulation devicebetween each time point is V_(com) as shown in the figure, this meansthat the black line scanning is performed on the display screen duringthis period, and by doing so, it can achieve the same results asinserting black frames or shutting off the backlights, so as to achievethe purpose of simulating CRT display impulse type image display.

In addition, the n shown at pulse G_(1′) in the Nth frame as shown inFIG. 8(c) indicates n pulses, which means that there exists the timedifference of n scanning lines between the control voltage pulse G₁ andG_(1′) in the same frame, namely, from the standpoint of the pixel,another control driving pulse G_(14′) will be input, at only nG₁ pulsesafter the first G₁ pulse. And this interval of time represented by n canbe properly adjusted by the designer depending on the actualrequirements such as the property of liquid crystal material etc., so asto ensure achieving the effectiveness of simulating CRT display impulsetype image display. And this is the most important advantage of thepresent invention over prior art.

For the sake of easy and convenient explanation and understanding, thewaveform of the driving voltage pulse V_(LC) output by the simulationdevice of the present Embodiment as shown above is the same as that ofEmbodiment 1, so as to avoid it being too complicated to understand inthe process of explanation. However, the waveform can be designed tohave various variations according to the actual requirements of the LCDdisplay.

Embodiment 4

In the following analyses, please refer to FIGS. 9(a), 9(b) and FIGS.10(a) to 10(d) as we explain fourth embodiment of the present invention.

First, please refer to FIG. 9(a), which indicates: the pixel arrayformed by the cross points of a plurality of gate lines and data lines,and the driving circuit formed by a plurality of data driver and gatedriver according to the fourth embodiment of the present invention. AndFIG. 9(b) represents the simulation device according to the fourthembodiment.

Simulation Device

According to FIGS. 9(a) and 9(b), the simulation device of the fourthEmbodiment comprises: a first input control line (G₁); a second inputcontrol line (G_(m)); a first input data line (D₁); a first capacitor(C_(S)); a second capacitor (C_(LS)); a driving voltage output line; anda first transistor (Q) comprising: a gate connected to the first inputcontrol line (G₁) or the second input control line (G_(m)), a sourceconnected to the input data line (D₁), and a drain connected to thedriving voltage output line and two capacitors (C_(S), C_(LS)) connectedin parallel; and wherein the said first capacitor and second capacitorare connected to ground, and the driving voltage output line is used tooutput the driving voltage used for simulation to the said pixels of theLCD panel so as to display images, and it is characterized in that thesaid input data line is connected to a data driver, the said inputcontrol line is connected to the gate driver, the said gate drivercontains: an output enable (OE) input line and a start pulse horizontal(STH) input line and receives the related signals via the said inputlines, so as to generate the synchronous control voltage pulses G₁,G_(m) of the said input control lines, and supply them to the gate ofthe said transistor via the first and second input control lines, and togenerate the driving voltage pulse V_(LC) through its control, and thenbe able to generate two synchronous scanning lines separated by mscanning lines on the display screen simultaneously, so as to displayimages.

Simulation Method

The following is the simulation method used for the simulation deviceaccording to the fourth embodiment of the present invention, comprisingthe following steps: (I) providing the data signal (D1) with periodicpulse waveform to the source of the said first transistor (Q1); (II)providing control signals OE and STH to the gate driver, so as togenerate the synchronous control signals G1, Gm and providing them tothe gate of the said transistor (Q1) via the first and second inputcontrol lines; (III) when activated by the said synchronous controlsignals G1, Gm, the said circuit feeds the said data signal to the saiddriving voltage output line; and (IV) outputting the said output drivingvoltage generated by the above steps to the said pixels so as to displayimages.

Waveform Analysis

In the following, please refer to FIGS. 10(a) to 10(d), as we describein detail the relations between the waveforms of the pulses of controlvoltages G₁, G_(m) and the pulses of the driving voltages D₁, V_(LC)generated by the simulation device of FIGS. 9(a) and 9(b) according thefourth embodiment of the present invention.

Since usually AC voltage is utilized as the driving voltage for drivingthe liquid crystal, this voltage indicates the phenomenon of alternatingpositive and negative phases during the control and driving process ofthe liquid crystal (namely, the waveforms of the pulses of drivingvoltages D₁ and V_(LC) indicate the phenomenon of alternating positiveand negative phases relative to the reference voltage V_(COM)).

These waveforms proceed sequentially and periodically from time pointsA1 to A6 repeatedly in the following manner:

The value of driving voltage pulse D₁ in the (N−1)th frame before timepoint A1 is V_(1′) (code 0), and the value of the driving voltage pulseV_(LC) is V_(1′) (code 0) of negative polarity; at time point A1, thewaveform enters the Nth frame, at this time the value of the drivingvoltage pulse D₁ increases to V2 (code 32), and due to the activation ofthe control voltage G₁, therefore the driving voltage pulse V_(LC)generated by the simulation device also increases to V₂ (code 32) ofpositive polarity and remains so until time point A2; then the timeproceeds to time point A2, at this time the value of driving voltagepulse D₁ is V₁ (code 0), and due to the activation of control voltagepulse G₁, resulting in the value of driving voltage pulse V_(LC) to dropmomentarily from V₂ (code 32) to V₁ (code 0) and is still of positivepolarity, and this value is maintained until time point A3; then thetime proceeds to time point A3 and enters the (N+1)th frame, at thistime the value of the driving voltage pulse D₁ drops to V_(3′) (code120) and is of negative polarity, and due to the activation of controlvoltage pulse G₁, the value of the driving voltage pulse V_(LC) alsomomentarily drops to V_(3″) (code 120) of negative polarity, and itremains so until time point A4; then time proceeds to A4, at this time,the value of driving voltage pulse D₁ is still V_(1′) (code 0), and dueto the activation of control voltage pulse G₁, resulting in the value ofthe driving voltage pulse V_(LC) also increases to V_(1′) (code 0) andis still of negative polarity until time point A5; then time proceeds totime point A5 and starts to enter the (N+2)th frame, at this time thevalue of the driving voltage pulse D₁ increases to V₃ (code 120), anddue to the activation of the control voltage pulse G₁, resulting in thevalue of the driving voltage pulse V_(LC) also increases momentarily toV₃ (code 120) of positive polarity, and it remains so until time pointA6.

The variations of control voltage pulses G₁, G_(1′) and driving voltagepulses D₁, and V_(LC) at the various time points after time points A6can easily be inferred based on the above descriptions.

The dotted line as shown in FIG. 10(a) is the liquid crystal displayoptical response characteristic curve produced while performing thesimulation drive. When the output driving voltage V_(LC) of thesimulation device between each time point is code 0 as shown in thefigure, this means that the black line scanning is performed on thedisplay screen during this period, and by doing so, it can achieve thesame results as inserting black frames or shutting off the backlights,so as to achieve the purpose of simulating CRT display impulse typeimage display.

The symbol Hsync in FIG. 10(c) indicates that the control voltage pulsesG₁ and G_(m) are synchronous signals.

Therefore, according to the design of the present Embodiment, G_(m) andG₁ are synchronous control voltage pulses. The scanning line generatedby the Gm control and the scanning line generated by G₁ control areseparated on the screen by m−1 scanning lines, and these two scanninglines execute scanning on the display screen in a synchronous manner.And the relations between the waveforms of control voltage pulse G_(m)and driving voltage pulse D₁, V_(LC) are the same as those between thewaveforms of control voltage pulse G₁ and driving voltage pulse D₁,V_(LC) (namely, the description above regarding FIGS. 10(a) to 10(d)),therefore, it will not be repeated here.

For the sake of easy and convenient explanation and understanding, thewaveform of the driving voltage pulse V_(LC) output by the simulationdevice of the present Embodiment as shown above is the same as that ofEmbodiment 1, so as to avoid it being too complicated to understand inthe process of explanation. However, the waveform can be designed tohave various variations according to the actual requirements of the LCDdisplay.

For the sake of easy and convenient explanation and understanding, thewaveform of the driving voltage pulse V_(LC) output by the simulationdevice of the present Embodiment as shown above is the same as that ofEmbodiment 1, so as to avoid it being too complicated to understand inthe process of explanation. However, the waveform can be designed tohave various variations according to the actual requirements of the LCDdisplay.

It must be particularly emphasized here that regardless of the positiveor negative polarity of the liquid crystal driving voltage pulse V_(LC),as long as it can attain the predetermined target level, then it is ableto achieve the purpose and effectiveness of accelerated driving of theoptical response of liquid crystal and simulating the CRT image display.

In addition, according to the design features of the present invention,the separation of m scanning lines between two subsequent controlvoltage pulses G₁ (FIG. 10(b)) and Gm (FIG. 10(c)) in the same frame(for example the Nth frame) can be adjusted depending on the actualeffectiveness desired to be achieved and the design requirements. Andthis is the important invention and feature of the present case, and itis not disclosed in all the related prior art.

Embodiment 5

In the following, please refer to FIGS. 11(a), 11(b) and FIGS. 12(a) to12(e) as we explain the fifth embodiment of the present invention. AndFIGS. 11(a) and 11(b) are used to describe the fifth Embodiment and thesubsequent sixth Embodiment of the present invention, its purpose is toindicate that: different image display effects can be achieved on thedisplay screen by utilizing different control methods with the samedevice, and this characteristic will be discussed as follows.

First, please refer to FIG. 11(a), which indicates: the pixel arrayformed by the cross points of a plurality of gate lines and data lines,and the driving circuit formed by a plurality of data driver and gatedriver according to the fifth embodiment of the present invention. AndFIG. 11(b) represents the simulation device according to the fifthembodiment.

Simulation Device

According to FIGS. 11(a) and 11(b), the simulation device of the fifthEmbodiment comprises: a first input control line (G₁); a second inputcontrol line (G_(m+1)); a third input control line (G_(2m+1)); a firstinput data line (D₁); a first capacitor (Cs); a second capacitor(C_(LS)); and a driving voltage output line; and a first transistor (Q)comprising a gate connected to the first input control line (G₁) or thesecond input control line (G_(m+1)) or the third input control line(G_(2m+1)); a source connected to the first input data line (D₁), and adrain connected to the driving voltage output line and two capacitors(C_(S), C_(LS)) connected in parallel; and wherein the said firstcapacitor and second capacitor are the storage capacitor and liquidcrystal equivalent capacitor respectively and connected to ground, andthe driving voltage output line is used to output the driving voltageused for simulation to the said pixels of the LCD panel so as to displayimages, and it is characterized in that, the said input data line isconnected to a data driver, the said input control line is connected tothe gate driver, the said gate driver contains: the first, the second,and the third output enable (OE) input lines and the first, the second,and the third start pulse horizontal (STH) input lines, and receives therelated signals via the said input lines, the said output enable (OE)signals input by the said gate drivers are so controlled that the twosets of synchronous control voltage pulses generated at the output ofthe said gate drivers are selected from the following three sets ofcontrol voltage pulses: (1) (G₁, G_(m)), (2) (G_(m+1), G_(2m)), (3)(G_(2m+1), G_(3m)); and these two sets of control voltage pulses (1, 3),or (1, 2), or (2, 3) are selected from the said three sets of controlvoltage pulses and then arranged and combined, such that they areprovided to the gate of the said transistors through the correspondingfirst, or second, or third input control line in a cyclic alternatingmanner, and the driving voltage pulse V_(LC) generated through thecontrol of the gate can be used to drive the pixels to simultaneouslygenerate two synchronous scanning lines separated by 2m scanning lineson the display screen in a cyclic alternating manner, so as to displayimages.

Simulation Method

The following is the simulation method used for the simulation deviceaccording to the fifth embodiment of the present invention, comprisingthe following steps: (I) providing the data signal (D1) with periodicpulse waveform to the source of the said first transistor (Q1); (II)providing the OE and STH control signals to the first, second, and thirdoutput enable (OE) input lines and start pulse horizontal (STH) inputlines of the said gate driver, and receiving the related signals via thesaid input lines, the said output enable (OE) signals input by the saidgate drivers are so controlled that the two sets of synchronous controlvoltage pulses generated at the output of the said gate drivers areselected from the following three sets of control voltage pulses: (1)(G₁, G_(m)), (2) (G_(m+1), G_(2m)), (3) (G_(2m+1), G_(3m)); and thesetwo sets of control voltage pulses (1,3), or (1, 2), or (2, 3) areselected from the said three sets of control voltage pulses and thenarranged and combined, such that they are provided to the gate of thesaid transistors (Q1) through the corresponding first, second, or thirdinput control lines in a cyclic alternating manner and it ischaracterized in that when activated by the said two sets of synchronouscontrol signals (1, 3), or (1, 2), or (2, 3), the said circuit feeds thesaid data signal to the said driving voltage output line; and (III)outputting the said output driving voltage generated by the above stepsto the said pixels, so as to simultaneously generate two synchronousscanning lines separated by 2m scanning lines on the display screen in acyclic alternating manner, so as to display images.

Waveform analysis

In the following analysis, please refer to FIGS. 12(a) to 12(e) as wedescribe in detail the relations between the waveforms of the pulses ofcontrol voltages (G₁, G_(m)), (G_(m+1), G_(2m)), (G_(2m+1), G_(3m)) andthe pulses of the driving voltages D₁, V_(LC) generated by thesimulation device of FIGS. 11(a) and 11(b) according the fifthembodiment of the present invention.

Since usually AC voltage is utilized as the driving voltage for drivingthe liquid crystal, therefore, this voltage indicates the phenomenon ofalternating positive and negative phases during the control and drivingprocess of the liquid crystal (namely, the waveforms of the pulses ofdriving voltages D₁, V_(LC) indicate the phenomenon of alternatingpositive and negative phases relative to the reference voltage V_(COM)).

These waveforms proceed sequentially and periodically from time pointsA1 to A6 repeatedly in the following manner:

The value of driving voltage pulse D₁ in the (N-1)th frame before timepoint A1 is V_(1′) (code 0), and the value of the driving voltage pulseV_(LC) is V_(1′) (code 0) of negative polarity; at time point A1, thewaveform enters the Nth frame, at this time the value of the drivingvoltage pulse D₁ increases to V₂ (code 32), and due to the activation ofthe control voltage G₁, therefore the value of output driving voltagepulse V_(LC) generated by the simulation device also increases to V₂(code 32) of positive polarity and it remains so until time point A2;then the time proceeds to time point A2, at this time the value ofdriving voltage pulse D₁ is V₁ (code 0), and due to the activation ofcontrol voltage pulse G₁, resulting in the value of driving voltagepulse V_(LC) to drop momentarily from V₂ (code 32) to V₁ (code 0) and isstill of positive polarity, and this value is maintained until timepoint A3; then the time proceeds to time point A3 and enters the (N+1)thframe, at this time the value of the driving voltage pulse D₁ drops toV_(3′) (code 120), and due to the activation of control voltage pulseG₁, the value of the driving voltage pulse V_(LC) also momentarily dropsto V_(3′) (code 120) of negative polarity, and it remains so until timepoint A4; then time proceeds to A4, at this time, the value of drivingvoltage pulse D₁ is still V_(1′) (code 0), and due to the activation ofcontrol voltage pulse G₁, resulting in the value of the driving voltagepulse V_(LC) also increases to V_(1′) (code 0) and is still of negativepolarity until time point A5; then time proceeds to time point A5 andstarts to enter the (N+2)th frame, at this time the value of the drivingvoltage pulse D₁ increases to V₃ (code 120), and due to the activationof the control voltage pulse G₁, resulting in the value of the drivingvoltage pulse V_(LC) also increases momentarily to V₃ (code 120) ofpositive polarity, and it remains so until time point A6.

The variations of control voltage pulses G_(m+1), G_(2m+1) and drivingvoltage pulses D₁, and V_(LC) at the various time points after timepoints A6 can easily be inferred based on the above descriptions.

The dotted line as shown in FIG. 12(a) is the liquid crystal displayoptical response characteristic curve produced while performing thesimulation drive. When the output driving voltage V_(LC) of thesimulation device between each time point is code 0 as shown in thefigure, this means that the black line scanning is performed on thedisplay screen during this period, and by doing so, it can achieve thesame results as inserting black frames or shutting off the backlights,so as to achieve the purpose of simulating CRT display impulse typeimage display.

For the sake of easy and convenient explanation and understanding, thewaveform of the driving voltage pulse V_(LC) output by the simulationdevice of the present Embodiment as shown above is the same as that ofEmbodiment 6, so as to avoid it being too complicated to understand inthe process of explanation. However, the waveform can be designed tohave various variations according to the actual requirements of the LCDdisplay.

In summary, the purpose of the present invention is to generate twosynchronous scanning lines on the display screen as shown in FIGS.12(b), 12(c) and 12(d). G₁, G_(m+1), G_(2m+1) are synchronous controlvoltage pulses, and two sets of scanning lines are generated on thedisplay screen by the driving voltage pulses generated through thecontrol of the said control voltage pulses, and are performedsynchronous scanning separated by 2m scanning lines so as to displayimages.

Embodiment 6

In the following analyses, please refer to FIGS. 11(a), 11(b) and FIGS.13(a) to 13(e) as we explain sixth embodiment of the present invention.And FIGS. 11(a) and 11(b) are used to describe the sixth Embodiment andthe preceding fifth Embodiment of the present invention, its purpose isto indicate that: different image display effects can be achieved on thedisplay screen by utilizing different control methods with the samedevice, and this characteristic will be discussed as follows.

First, please refer to FIG. 11(a), which indicates: the pixel arrayformed by the cross points of a plurality of gate lines and data lines,and the driving circuit formed by a plurality of data driver and gatedriver according to the sixth embodiment of the present invention. AndFIG. 11(b) represents the simulation device according to the sixthembodiment.

Simulation Device

According to FIGS. 11(a) and 11(b), the simulation device of the sixthEmbodiment comprises: a first input control line (G₁); a second inputcontrol line (G_(m+1); a third input control line (G₂₊₁); a first inputdata line (D₁); a first capacitor (Cs); a second capacitor (C_(LS)); adriving voltage output line; and a first transistor (Q) comprising agate connected to the first input control line (G₁) or the second inputcontrol line (G_(m+1)) or the third input control line (G_(2m+1)); asource connected to the first input data line (D₁), and a drainconnected to the driving voltage output line and two capacitors (C_(S),C_(LS)) connected in parallel; wherein the said first capacitor andsecond capacitor are the storage capacitor and liquid crystal equivalentcapacitor respectively and connected to ground, and the driving voltageoutput line is used to output the driving voltage used for simulation tothe said pixels of the LCD panel so as to display images, and it ischaracterized in that the said input data line is connected to a datadriver, the said input control line is connected to the gate driver, thesaid gate driver contains: the first, the second, and the third outputenable (OE) input lines and the first, the second, and the third startpulse horizontal (STH) input lines, and receives the related signals viathe said input lines, the said output enable (OE) signals input by thesaid gate drivers are so controlled that the three sets of synchronouscontrol voltage pulses generated at the output of the said gate driversare formed by and selected from the following three sets of controlvoltage pulses: (1) (G₁, G_(m)), (2) (G_(m+1), G_(2m)), (3) (G_(2m+1),G_(3m)); and these three sets control voltage pulses (1, 2, 3) areprovided to the gate of the said transistors (Q1) through thecorresponding first, or second, and third input control lines, and it ischaracterized in that when activated by the said three sets ofsynchronous control signals (1, 2, 3) the said circuit feeds the saiddata signal to the said driving voltage output line; and the drivingvoltage pulse V_(LC) generated through the control of the gate can beused to drive the pixels to simultaneously generate three synchronousscanning lines separated by m scanning lines on the display screen, soas to display images.

Simulation Method

The following is the simulation method used for the simulation deviceaccording to the sixth embodiment of the present invention, comprisingthe following steps: (1) providing the data signal (D1) with periodicpulse waveform to the source of the said first transistor (Q1); (II)providing the OE and STH control signals to the first, second, and thirdoutput enable (OE) input lines and start pulse horizontal (STH) inputlines of the said gate driver, and receiving the related signals via thesaid input lines, the said output enable (OE) signals input by the saidgate drivers are so controlled that the three sets of synchronouscontrol voltage pulses generated at the output of the said gate driversare selected from the following three sets of control voltage pulses:(1) (G₁, G_(m)), (2) (G_(m+1), G_(2m)), (3) (G₂₊₁, G_(3m)); and thesethree sets of control voltage pulses (1,2,3) are provided to the gate ofthe said transistors (Q1) through the corresponding first, second andthird input control lines, and it is characterized in that whenactivated by the said three sets of synchronous control signals (1, 2,3), the said circuit feeds the said data signal to the said drivingvoltage output line; and (III) outputting the said output drivingvoltage generated by the above steps to the said pixels, so as tosimultaneously generate three synchronous scanning lines separated by mscanning lines on the display screen in a cyclic alternating manner, soas to display images.

Waveform Analysis

In the following analysis, please refer to FIGS. 13(a) to 13(e) as wedescribe in detail the relations between the waveforms of the pulses ofcontrol voltages (G₁, G_(m)), (G_(m+1), G_(2m)), (G_(2m+1), G_(3m)) andthe pulses of the driving voltages D₁, V_(LC) generated by thesimulation device of FIGS. 11(a) and 11(b) according the sixthembodiment of the present invention.

Since usually AC voltage is utilized as the driving voltage for drivingthe liquid crystal, this voltage indicates the phenomenon of alternatingpositive and negative phases during the control and driving process ofthe liquid crystal (namely, the waveforms of the pulses of drivingvoltages D₁, V_(LC) indicate the phenomenon of alternating positive andnegative phases relative to the reference voltage V_(COM)).

These waveforms proceed sequentially and periodically from time pointsA1 to A6 repeatedly in the following manner:

The value of driving voltage pulse D₁ in the (N-1)th frame before timepoint A1 is V_(1′) (code 0), and the value of the driving voltage pulseV_(LC) is V_(1′) (code 0) of negative polarity; at time point A1, thewaveform enters the Nth frame, at this time the value of the drivingvoltage pulse D₁ increases to V2 (code 32), and due to the activation ofthe control voltage G₁, therefore the value of output driving voltagepulse V_(LC) generated by the simulation device also increases to V₂(code 32) of positive polarity and it remains so until time point A2;then the time proceeds to time point A2, at this time the value ofdriving voltage pulse D₁ is V₁ (code 0), and due to the activation ofcontrol voltage pulse G₁, resulting in the value of driving voltagepulse V_(LC) to drop momentarily from V₂ (code 32) to V₁ (code 0) and isstill of positive polarity, and this value is maintained until timepoint A3; then the time proceeds to time point A3 and enters the (N+1)thframe, at this time the value of the driving voltage pulse D₁ drops toV_(3′) (code 120), and due to the activation of control voltage pulseG₁, the value of the driving voltage pulse V_(LC) also momentarily dropsto V_(3′) (code 120) of negative polarity, and it remains so until timepoint A4; then time proceeds to A4, at this time, the value of drivingvoltage pulse D₁ is still V_(1′) (code 0), and due to the activation ofcontrol voltage pulse G₁, resulting in the value of the driving voltagepulse V_(LC) also increases to V_(1′) (code 0) and is still of negativepolarity until time point A5; then time proceeds to time point A5 andstarts to enter the (N+2)th frame, at this time the value of the drivingvoltage pulse D₁ increases to V₃ (code 120), and due to the activationof the control voltage pulse G₁, resulting in the value of the drivingvoltage pulse V_(LC) also increases momentarily to V₃ (code 120) ofpositive polarity, and it remains so until time point A6.

The variations of control voltage pulses G_(m+1), G_(2m+1) and drivingvoltage pulses D₁, and V_(LC) at the various time points after timepoints A6 can easily be inferred based on the above descriptions.

The dotted line as shown in FIG. 13(a) is the liquid crystal displayoptical response characteristic curve produced while performing thesimulation drive. When the output driving voltage V_(LC) of thesimulation device between each time point is code 0 as shown in thefigure, this means that the black line scanning is performed on thedisplay screen during this period, and by doing so, it can achieve thesame results as inserting black frames or shutting off the backlights,so as to achieve the purpose of simulating CRT display impulse typeimage display.

In summary, the purpose of the present invention is to generate threesynchronous scanning lines on the display screen as shown in FIGS.13(b), 13(c) and 13(d). G₁, G_(m+1), G_(2m+1) are synchronous controlvoltage pulses, and three sets of scanning lines are generated on thedisplay screen by the driving voltage pulses generated through thecontrol of the said control voltage pulses, and perform the synchronousline scanning on the screen separated by m scanning lines so as todisplay images.

Therefore, according to the design of the present invention, G_(m+1) andG₁ are synchronous control voltage pulses, and the scanning linesgenerated through the control of G_(m+1) and the scanning linesgenerated through the control of G₁ are separated by m scanning lines onthe screen, and these two sets of scanning lines perform scanning on thescreen in a synchronous manner, namely, start scanning on the screenfrom the first and the (m+1)th scanning lines respectively. Therelations between the waveforms of the control voltage pulses G_(m+1)and the driving voltage pulses D₁, V_(LC) are the same as those betweenwaveforms of the control voltage pulse G1 and the driving voltage pulsesD₁, V_(LC) (namely, as explained above with reference to FIGS. 13(a) to13(e)), therefore, it will not be repeated here.

And at the same time, the corresponding driving voltage pulses generatedby the control voltage pulses (G_(m+1), G_(2m)), (G_(2m+1), G_(2m)), andthe resulting scanning lines generated on the screen, start scanninglines generated on the screen, start scanning from the (m+1)th, (2m+1)th scanning lines downward on the screen respectively in asynchronous manner (namely, the three sets of scanning lines generatedon the display screen by the present embodiment, start scanning downwardsynchronously from the first, (m+1)th and (2 m+1)th scanning lines in arepeated cyclic manner). And the relations between the waveforms of therespective control voltage pulses (G_(m+1), G_(2m)), (G_(2m+1), G_(3m))and the driving voltage pulses D₁, V_(LC) are the same as those betweenthe waveforms of the respective control voltage pulses (G₁, G_(m)) anddriving voltage pulse D₁, V_(LC) (namely, as explained above withreference to FIGS. 13(a) to 13(e)). Therefore, it will not repeatedhere.

For the sake of easy and convenient explanation and understanding, thewaveform of the driving voltage pulse V_(LC) output by the simulationdevice of the present Embodiment as shown above is the same as that ofEmbodiment 1, so as to avoid it being too complicated to understand inthe process of explanation. However, the waveform can be designed tohave various variations according to the actual requirements of the LCDdisplay.

As it is known from the detailed description of the above sixembodiments of the present invention that, the method and device of thepresent invention are characterized in that, the scanning black lines asdescribed above can also achieve the similar effects of writing blackframes, blinking backlights, or the combination of this two methods ofthe prior art, so as to simulate the CRT impulse type image display withLCD display, and apparently it is superior to the prior art for thefollowing reasons:

-   -   (1) The present invention can save the extra cost and expense of        the additional frequency doubling device or the backlight        blinking equipment as required by the prior art;    -   (2) The present invention can avoid the electric magnetic        interference induced by the additional equipment;    -   (3) The especially important feature of the present invention        is, the interval between two input control voltage pulses G1 and        G1′ whinin the duration of the same frame can be adjusted        depending on the actual requirements, so as to make the duration        of the liquid crystal optical gray level response and the black        line scanning (especially the black line scanning) adjustable in        the duration of the same frame. Therefore, the designer of the        LCD display is able to adjust the duration of the black line        scanning depending on the time required by the optical response        characteristic of different liquid crystal material, and the        present invention can not only provide adequate design        flexibility, but can also eliminate thoroughly the phenomenon of        images superposition and outlines blurring created by the “after        image” of the prior art, so as to optimize the quality of the        images displayed. Therefore, the present invention can indeed        achieve the purpose and the effectiveness of simulating the CRT        impulse type image display with LCD display. The description        above indicates all the features of the present invention        superior to those of the prior art.

Summing up the above, the method and device utilized by the presentinvention in simulating the CRT impulse type image display can indeedovercome and improve the drawbacks and limitations of the similar liquidcrystal display of the prior art, it can save the extra cost and expenseof the additional equipment and significantly improve its functions.Therefore, the method and device used by the present invention insimulating the CRT impulse type image display is indeed superior tothose of the prior art. The present invention does have the value ofutilization in the industry, and it does contain novelty and inventivesteps, and it is in conformity with the patent requirements.

The description mentioned above only relates to the preferredEmbodiments of the present invention, and it is intended to beillustrative rather than restrictive to the contents of the claims andthe present invention; and various changes and modifications can be madeby the people familiar with this technology without departing from thescope of the present invention and the appended claims.

1. A device used for simulating CRT impulse type image display,comprising: a first input control line; a second input control line; afirst input data line; a second input data line; a first capacitor; asecond capacitor; a driving voltage output line; a first transistor,comprising: a first gate connected to the first input control line, afirst source connected to the first input data line, and a first drainconnected to the driving voltage output line and the first capacitor andthe drain of the second transistor; and a second transistor, comprising:a second gate connected to the second input control line, a secondsource connected to the second input data line, a second drain connectedto the drain of the said first transistor and the second capacitor anddriving voltage output line; wherein the said first capacitor and thesaid second capacitor are storage capacitor and liquid crystalequivalent capacitor respectively and are connected to ground, and thedriving voltage output line is used to output the driving voltage usedfor simulation to the said pixels of the LCD panel so as to displayimages; and characterized in that the said first and second inputcontrol lines are connected to a gate driver, and the said first andsecond input data lines are connected to a data driver respectively. 2.A method used for simulating CRT impulse type image display, comprisingthe following steps: (1) providing a circuit comprising a first inputcontrol line, a second input control line, a first input data line, asecond input data line, a first transistor, a second transistor, a firstcapacitor, a second capacitor, and a driving voltage output line; (2)providing the first control signal with periodic pulse waveforms to thefirst gate of the first transistor of the said circuit; (3) providingthe second control signal with periodic pulse waveforms to the secondgate of the second transistor of the said circuit; (4) the secondcontrol signal is the same as the first control signal except the phasedelay; (5) providing the first data signal to the source of the firsttransistor of the said circuit, when activated by the said first controlsignal, the said circuit feeds the first data signal to the said drivingvoltage output line; (6) providing the second data signal to the sourceof the second transistor of the said circuit, when activated by the saidsecond control signal, the said circuit feeds the second data signal tothe said driving voltage output line; and (7) outputting the said outputdriving voltages generated by the above steps to the said pixels, so asto display images.
 3. The method as claimed in claim 2, wherein since ACvoltage is used as the control voltage and driving voltage, thesevoltages indicate the phenomenon of alternating positive and negativephases during their control and driving processes, and their waveformsproceed sequentially and periodically from time points A1 to A6repeatedly in the following manner: (a) the value of driving voltagepulse D_(1′) in the (N−1)th frame before time point A1 is V_(1′), andthe value of the driving voltage pulse V_(LC) is V_(1′) of negativepolarity; (b) at time point A1, the waveform enters the Nth frame, atthis time the value of the driving voltage pulse D₁ increases to V2, anddue to the activation of the control voltage pulse G₁, therefore thevalue of driving voltage pulse V_(LC) generated by the simulation devicealso increases to V₂ of positive polarity and remains so until timepoint A2; (c) then the time proceeds to time point A2, at this time thevalue of driving voltage pulse D_(1′) is V₁, and due to the activationof control voltage pulse G_(1′), resulting in the value of drivingvoltage pulse V_(LC) to drop momentarily from V₂ to V₁ and is still ofpositive polarity, and this value is maintained until time point A3; (d)then the time proceeds to time point A3 and enters the (N+1)th frame, atthis time the value of the driving voltage pulse D₁ drops to V_(3′), andis of negative polarity, and due to the activation of control voltagepulse G₁, the value of the driving voltage pulse V_(LC) also momentarilydrops to V_(3′) of negative polarity, and it remains so until time pointA4; (e) then time proceeds to A4, and at this time, the value of drivingvoltage pulse D_(1′) is still V_(1′), and due to the activation ofcontrol voltage pulse G_(1′), resulting in the value of the drivingvoltage pulse V_(LC) also increases to V_(1′) and is still of negativepolarity and it remains so until time point A5; and (f) then timeproceeds to time point A5 and starts to enter the (N+2)th frame, at thistime the value of the driving voltage pulse D₁ increases to V₃, and dueto the activation of the control voltage pulse G₁, resulting in thevalue of the driving voltage pulse V_(LC) also increases momentarily toV₃ of positive polarity, and it remains so until time point A6.
 4. Themethod as claimed in claim 3, wherein when the output driving voltageV_(LC) of the simulation device between each time point is code 0, thismeans that the black line scanning is performed on the display screenduring this period, and it can achieve the better results than insertingblack frames or shutting off the backlights, so as to optimally realizethe purpose of simulating CRT display impulse type image display withLCD display.
 5. A device used for simulating CRT impulse type imagedisplay, comprising: a first input control line; a second input controlline; a first input data line; a second input data line; a third inputdata line; a fourth input data line; a fifth input data line; a firstcapacitor; a second capacitor; a third transistor; a fourth transistor;driving voltage output line; a first transistor, comprising: a firstgate connected to the first input control line, a first source connectedto the input data line, and a first drain connected to the drivingvoltage output line and the first capacitor and the drain of the secondtransistor; and a second transistor, comprising: a second gate connectedto the second input control line, a second source connected to thesecond input data line, a second drain connected to the drain of thesaid first transistor and the second capacitor and driving voltageoutput line; wherein the said first capacitor and the said secondcapacitor are storage capacitor and liquid crystal equivalent capacitorrespectively and are connected to ground, and the driving voltage outputline is used to output the driving voltage used for simulation to thesaid pixels of the LCD panel so as to display images, characterized inthat the said first and second input control lines are connected to agate driver, and the said first and second input data lines areconnected to the drains of two another switching transistors connectedin parallel, the sources of the said two switching transistors connectedin parallel are connected to a data driver, with its gate connected tothe third and fourth input data lines, and the time difference betweenthe periodic pulse waveforms of the said first and second controlsignals is the time difference across n scanning lines generated by npulses, and which can be adjusted.
 6. A method used for simulating CRTimpulse type image display, comprising the following steps: (1)providing a circuit, comprising a first input control line, a secondinput control line, a first input data line, a second input data line, athird input data line, a fourth input data line, a fifth input dataline, a first transistor, a second transistor, a third transistor, afourth transistor, a first capacitor, a second capacitor, and a drivingvoltage output line; (2) providing the first control signal withperiodic pulse waveforms to the first gate of the first transistor ofthe said circuit; (3) providing the second control signal with periodicpulse waveforms to the second gate of the second transistor of the saidcircuit; (4) the second control signal is the same as the first controlsignal except the phase delay; (5) providing the fifth data signal tothe sources of the third transistor and fourth transistor connected inparallel; (6) providing the third data signal to the gate of the thirdtransistor; (7) providing the voltage pulse generated by the drain ofthe third transistor to the source of the first transistor as the firstdata signal, when the said first transistor is activated by the firstcontrol signal, the first data signal is fed by the said circuit to thedriving voltage output line; (8) providing the fourth data signal to thegate of the fourth transistor; (9) providing the voltage pulse generatedby the drain of the fourth transistor to the source of the secondtransistor as the second data signal, when the said second transistor isactivated by the second control signal, the second data signal is fed bythe said circuit to the driving voltage output line; and (10) outputtingthe said output driving voltage generated by the above steps to the saidpixels so as to display images.
 7. The method as claimed in claim 6,wherein since AC voltage is used as the control voltage and drivingvoltage, these voltages indicate the phenomenon of alternating positiveand negative phases during their control and driving processes, andtheirwaveforms proceed sequentially and periodically from time points A1to A6 repeatedly in the following manner: (a) the value of drivingvoltage pulse D_(1′) in the (N−1)th frame before time point A1 isV_(1′), and the value of the driving voltage pulse V_(LC) is V_(1′) ofnegative polarity; (b) at time point A1, the waveform enters the Nthframe, at this time the value of the driving voltage pulse D₁ increasesto V2, and due to the activation of the control voltage pulse G₁,therefore the value of driving voltage pulse V_(LC) generated by thesimulation device also increases to V₂ of positive polarity and remainsso until time point A2; (c) then the time proceeds to time point A2, atthis time the value of driving voltage pulse D_(1′) is V₁, and due tothe activation of control voltage pulse G_(1′), resulting in the valueof driving voltage pulse V_(LC) to drop momentarily from V₂ to V₁ and isstill of positive polarity, and this value is maintained until timepoint A3; (d) then the time proceeds to time point A3 and enters the(N+1)th frame, at this time the value of the driving voltage pulse D₁drops to V_(3′) and is of negative polarity, and due to the activationof control voltage pulse G₁, the value of the driving voltage pulseV_(LC) also momentarily drops to V_(3′) of negative polarity, and itremains so until time point A4; (e) then time proceeds to A4, at thistime, the value of driving voltage pulse D_(1′) is still V_(1′), and dueto the activation of control voltage pulse G_(1′), resulting in thevalue of the driving voltage pulse V_(LC) also increases to V_(1′) andis still of negative polarity and it remains so until time point A5; and(f) then time proceeds to time point A5 and starts to enter the (N+2)thframe, at this time the value of the driving voltage pulse D₁ increasesto V₃, and due to the activation of the control voltage pulse G₁,resulting in the value of the driving voltage pulse V_(LC) alsoincreases momentarily to V₃ of positive polarity, and it remains sountil time point A6.
 8. The method as claimed in claim 7, wherein whenthe output driving voltage V_(LC) of the simulation device between eachtime point is code 0, this means that the black line scanning isperformed on the display screen during this period, and it can achievethe better results than inserting black frames or shutting off thebacklights, so as to optimally realize the purpose of simulating CRTdisplay impulse type image display with LCD display.
 9. A device usedfor simulating CRT impulse type image display, comprising: a first inputcontrol line; a second input control line; a first input data line; afirst capacitor; a second capacitor; driving voltage output line; afirst transistor, comprising: a first gate connected to the first inputcontrol line, a first source connected to the first input data line, anda first drain connected to the driving voltage output line and the firstcapacitor and the second drain of the second transistor; and a secondtransistor, comprising: a second gate connected to the second inputcontrol line, a second source connected to ground, a second drainconnected to the drain of the said first transistor and the secondcapacitor and driving voltage output line; wherein the said firstcapacitor and the said second capacitor are storage capacitor and liquidcrystal equivalent capacitor respectively and are connected to ground,and the driving voltage output line is used to output the drivingvoltage used for simulation to the said pixels of the LCD panel so as todisplay images, characterized in that the said first and second inputcontrol lines are connected to a gate driver, and the said first inputdata line is connected to a data driver; and the time difference betweenthe waveforms of the periodic pulses of the first and second controlsignals is the time difference across n scanning lines generated by npulses, and which can be adjusted.
 10. A method used for simulating CRTimpulse type image display, comprising the following steps: (1)providing a circuit, comprising a first input control line, a secondinput control line, a first input data line, a first transistor, asecond transistor, a first capacitor, a second capacitor, and a drivingvoltage output line; (2) providing the first control signal withperiodic pulse waveforms to the first gate of the first transistor ofthe said circuit; (3) providing the second control signal with periodicpulse waveforms to the second gate of the second transistor of the saidcircuit, wherein the second control signal is the same as the firstcontrol signal except the phase delay; (4) providing the first datasignal to the source of the first transistor of the said circuit, whenactivated by the said first control signal, the said circuit feeds thefirst data signal to the said driving voltage output line; (5) whenactivated by the second control signal, the ground potential voltage isfed by the said circuit to the driving voltage output line; and (6)outputting the said output driving voltages generated by the above stepsto the said pixels so as to display images.
 11. The method as claimed inclaim 10, wherein since AC voltage is used as the control voltage anddriving voltage, these voltages indicate the phenomenon of alternatingpositive and negative phases during their control and driving processes,and their waveforms proceed sequentially and periodically from timepoints A1 to A6 repeatedly in the following manner: (a) the value ofdriving voltage pulse D₁ in the (N−1)th frame before time point A1 isV₂′, and the value of the driving voltage pulse V_(LC) is V_(com) (sincethe source of the second transistor is connected to V_(com)); (b) attime point A1, the waveform enters the Nth frame, at this time the valueof the driving voltage pulse D₁ increases to V2, and due to theactivation of the control voltage pulse G₁, therefore the value ofdriving voltage pulse V_(LC) generated by the simulation device alsoincreases to V₂ of positive polarity and it remains so until time pointA2; (c) then the time proceeds to time point A2, at this time the valueof driving voltage pulse D₁ is still V₂, and due to the activation ofcontrol voltage pulse G_(1′) (since the source of the second transistoris connected to V_(com)), resulting in the value of driving voltagepulse V_(LC) to drop momentarily from V₂ to V₁ and is still of positivepolarity, and this value is maintained until time point A3; (d) then thetime proceeds to time point A3 and enters the (N+1)th frame, at thistime the value of the driving voltage pulse D₁ drops to V_(3′) and is ofnegative polarity, and due to the activation of control voltage pulseG₁, the value of the driving voltage pulse V_(LC) also momentarily dropsto V_(3′) of negative polarity, and it remains so until time point A4;(e) then time proceeds to time point A4, at this time, the value ofdriving voltage pulse D₁ is still V_(3′) of negative polarity, and dueto the activation of control voltage pulse G_(1′) (since the source ofthe second transistor is connected to V_(com)), resulting in the valueof the driving voltage pulse V_(LC) also increases to V_(com) and isstill of negative polarity and it remains so until time point A5; and(f) then time proceeds to time point A5 and it starts to enter the(N+2)th frame, at this time the value of the driving voltage pulse D₁increases to V₃, and due to the activation of the control voltage pulseG₁, resulting in the value of the driving voltage pulse V_(LC) alsoincreases momentarily to V₃ of positive polarity, and it remains sountil time point A6.
 12. The method as claimed in claim 11, wherein whenthe output driving voltage V_(LC) of the simulation device between eachtime point is code 0, this means that the black line scanning isperformed on the display screen during this period, and it can achievethe better results than inserting black frames or shutting off thebacklights, so as to optimally realize the purpose of simulating CRTdisplay impulse type image display with LCD display.
 13. A device usedfor simulating CRT impulse type image display, comprising: a first inputcontrol line; a second input control line; a first input data line; afirst capacitor; a second capacitor; a driving voltage output line; afirst transistor, comprising: a gate connected to the first inputcontrol line or the second input control line, a source connected to theinput data line, and a drain connected to the driving voltage outputline and two capacitors connected in parallel; and wherein the saidfirst capacitor and second capacitor are connected to ground, and thedriving voltage output line is used to output the driving voltage usedfor simulation to the said pixels of the LCD panel so as to displayimages, characterized in that the said input data line is connected to adata driver, the said input control line is connected to the gatedriver, the said gate driver contains: an output enable (OE) input lineand a start pulse horizontal (STH) input line and receives the relatedsignals via the said input lines, so as to generate the synchronouscontrol voltage pulses G₁, G_(m) of the said input control lines, andsupply them to the gate of the said transistor via the first and secondinput control lines, and to generate the driving voltage pulse V_(LC)through its control, and then be able to generate two synchronousscanning lines separated by m scanning lines on the display screensimultaneously, so as to display images.
 14. A method used forsimulating CRT impulse type image display, comprising the followingsteps: (1) providing a circuit, comprising a first input control line, asecond input control line, a first input data line, a first transistor,a first capacitor, a second capacitor, and a driving voltage outputline; (2) providing the data signal with periodic pulse waveform to thesource of the said first transistor; (3) providing control signals OEand STH to the gate driver, so as to generate the synchronous controlsignals G1, Gm, and providing them to the gate of the said transistorvia the first and second input control lines; (4) when activated by thesaid synchronous control signals G1, Gm, the said circuit feeds the saiddata signal to the said driving voltage output line; and (5) outputtingthe said output driving voltage generated by the above steps to the saidpixels so as to display images.
 15. The method as claimed in claim 14,wherein since AC voltage is used as the control voltage and drivingvoltage, these voltages indicate the phenomenon of alternating positiveand negative phases during their control and driving processes, andtheir waveforms proceed sequentially and periodically from time pointsA1 to A6 repeatedly in the following manner: (a) the value of drivingvoltage pulse D₁ in the (N−1)th frame before time point A1 is V_(1′),and the value of the driving voltage pulse V_(LC) is V_(1′) of negativepolarity; (b) at time point A1, the waveform enters the Nth frame, atthis time the value of the driving voltage pulse D₁ increases to V2, anddue to the activation of the control voltage G₁, therefore the drivingvoltage pulse V_(LC) generated by the simulation device also increasesto V₂ of positive polarity and remains so until time point A2; (c) thenthe time proceeds to time point A2, at this time the value of drivingvoltage pulse D₁ is V₁, and due to the activation of control voltagepulse G₁, resulting in the value of driving voltage pulse V_(LC) to dropmomentarily from V₂ to V₁ and is still of positive polarity, and thisvalue is maintained until time point A3; (d) then the time proceeds totime point A3 and enters the (N+1)th frame, at this time the value ofthe driving voltage pulse D₁ drops to V_(3′) and is of negativepolarity, and due to the activation of control voltage pulse G₁, thevalue of the driving voltage pulse V_(LC) also momentarily drops toV_(3′) of negative polarity, and it remains so until time point A4; (e)then time proceeds to A4, at this time, the value of driving voltagepulse D₁ is still V_(1′), and due to the activation of control voltagepulse G₁, resulting in the value of the driving voltage pulse V_(LC)also increases to V_(1′) and is still of negative polarity until timepoint A5; and (f) then time proceeds to time point A5 and starts toenter the (N+2)th frame, at this time the value of the driving voltagepulse D₁ increases to V₃, and due to the activation of the controlvoltage pulse G₁, resulting in the value of the driving voltage pulseV_(LC) also increases momentarily to V₃ of positive polarity, and itremains so until time point A6.
 16. The method as claimed in claim 15,wherein when the output driving voltage V_(LC) of the simulation devicebetween each time point is code 0, this means that the black linescanning is performed on the display screen during this period, and itcan achieve the better results than inserting black frames or shuttingoff the backlights, so as to optimally realize the purpose of simulatingCRT display impulse type image display with LCD display.
 17. A deviceused for simulating CRT impulse type image display, comprising: a firstinput control line; a second input control line; a third input controlline; a first input data line; a first capacitor; a second capacitor; adriving voltage output line; and a first transistor comprising: a gateconnected to the first input control line or the second input controlline or the third input control line; a source connected to the firstinput data line, and a drain connected to the driving voltage outputline and two capacitors connected in parallel; and wherein the saidfirst capacitor and second capacitor are the storage capacitor andliquid crystal equivalent capacitor respectively and connected toground, and the driving voltage output line is used to output thedriving voltage used for simulation to the said pixels of the LCD panelso as to display images, characterized in that the said input data lineis connected to a data driver, the said input control line is connectedto the gate driver, the said gate driver contains: the first, thesecond, and the third output enable (OE) input lines and the first, thesecond, and the third start pulse horizontal (STH) input lines, andreceives the related signals via the said input lines, the said outputenable (OE) signals input by the said gate drivers are so controlledthat the two sets of synchronous control voltage pulses generated at theoutput of the said gate drivers are selected from the following threesets of control voltage pulses: (1) (G₁, G_(m)), (2) (G_(m+1), G_(2m)),(3) (G_(2m+1), G_(3m)); and these two sets of control voltage pulses (1,3), or (1, 2), or (2, 3) are selected from the said three sets ofcontrol voltage pulses and then arranged and combined, such that theyare provided to the gate of the said transistors through thecorresponding first, or second, or third input control line in a cyclicalternating manner, and the driving voltage pulse V_(LC) generatedthrough the control of the gate can be used to drive the pixels tosimultaneously generate two synchronous scanning lines separated by 2mscanning lines on the display screen in a cyclic alternating manner, soas to display images.
 18. A method used for simulating CRT impulse typeimage display, comprising the following steps: (1) providing a circuitcomprising: a first input control line, second input control line, athird input control line, a first input data line, a first transistor, afirst capacitor, a second capacitor, and a driving voltage output line;(2) providing the data signal with periodic pulse waveform to the sourceof the said first transistor; (3) providing the OE and STH controlsignals to the first, second, and third output enable (OE) input linesand start pulse horizontal (STH) input lines of the said gate driver;and (4) receiving the related signals via the said input lines, the saidoutput enable (OE) signals input by the said gate drivers are socontrolled that the two sets of synchronous control voltage pulsesgenerated at the output of the said gate drivers are selected from thefollowing three sets of control voltage pulses: (1) (G₁, G_(m)), (2)(G_(m+1), G_(2m)), (3) (G₂ m+1, G_(3m)); and these two sets of controlvoltage pulses (1, 3), or (1, 2), or (2, 3) are selected from the saidthree sets of control voltage pulses and then arranged and combined,such that they are provided to the gate of the said transistors throughthe corresponding first, second, or third input control lines in acyclic alternating manner; characterized in that when activated by thesaid two sets of synchronous control signals (1, 3), or (1, 2), or (2,3), the said circuit feeds the said data signal to the said drivingvoltage output line; and outputting the said output driving voltagegenerated by the above steps to the said pixels, so as to simultaneouslygenerate two synchronous scanning lines separated by 2m scanning lineson the display screen in a cyclic alternating manner, so as to displayimages.
 19. The method as claimed in claim 18, wherein since AC voltageis used as the control voltage and driving voltage, these voltagesindicate the phenomenon of alternating positive and negative phasesduring their control and driving processes, and their waveforms proceedsequentially and periodically from time points A1 to A6 repeatedly inthe following manner: (a) the value of driving voltage pulse D₁ in the(N−1)th frame before time point A1 is V_(1′), and the value of thedriving voltage pulse V_(LC) is V_(1′) of negative polarity; (b) at timepoint A1, the waveform enters the Nth frame, at this time the value ofthe driving voltage pulse D₁ increases to V2, and due to the activationof the control voltage G₁, therefore the value of output driving voltagepulse V_(LC) generated by the simulation device also increases to V₂ ofpositive polarity and it remains so until time point A2; (c) then thetime proceeds to time point A2, at this time the value of drivingvoltage pulse D₁ is V₁, and due to the activation of control voltagepulse G₁, resulting in the value of driving voltage pulse V_(LC) to dropmomentarily from V₂ to V₁ and is still of positive polarity, and thisvalue is maintained until time point A3; (d) then the time proceeds totime point A3 and enters the (N+1)th frame, at this time the value ofthe driving voltage pulse D₁ drops to V₃′, and due to the activation ofcontrol voltage pulse G₁, the value of the driving voltage pulse V_(LC)also momentarily drops to V_(3′) of negative polarity, and it remains sountil time point A4; (e) then time proceeds to A4, at this time, thevalue of driving voltage pulse D₁ is still V_(1′), and due to theactivation of control voltage pulse G₁, resulting in the value of thedriving voltage pulse V_(LC) also increases to V_(1′) and is still ofnegative polarity until time point A5; and (f) then time proceeds totime point A5 and starts to enter the (N+2)th frame, at this time thevalue of the driving voltage pulse D₁ increases to V₃, and due to theactivation of the control voltage pulse G₁, resulting in the value ofthe driving voltage pulse V_(LC) also increases momentarily to V₃ ofpositive polarity, and it remains so until time point A6.
 20. The methodas claimed in claim 19, wherein when the output driving voltage V_(LC)of the simulation device between each time point is code 0, this meansthat the black line scanning is performed on the display screen duringthis period, and it can achieve the better results than inserting blackframes or shutting off the backlights, so as to optimally realize thepurpose of simulating CRT display impulse type image display with LCDdisplay.
 21. A device used for simulating CRT impulse type imagedisplay, comprising: a first input control line; a second input controlline; a third input control line; a first input data line; a firstcapacitor; a second capacitor; a driving voltage output line; and afirst transistor comprising: a gate connected to the first input controlline or the second input control line or the third input control line; asource connected to the first input data line, and a drain connected tothe driving voltage output line and two capacitors connected inparallel; and wherein the said first capacitor and second capacitor arethe storage capacitor and liquid crystal equivalent capacitorrespectively and connected to ground, and the driving voltage outputline is used to output the driving voltage used for simulation to thesaid pixels of the LCD panel so as to display images; characterized inthat the said input data line is connected to a data driver, the saidinput control the said input data line is connected to a data driver,the said input control line is connected to the gate driver, the saidgate driver contains: the first, the second, and the third output enable(OE) input lines and the first, the second, and the third start pulsehorizontal (STH) input lines, and receives the related signals via thesaid input lines, the said output enable (OE) signals input by the saidgate drivers are so controlled that the three sets of synchronouscontrol voltage pulses generated at the output of the said gate driversare formed by and selected from the following three sets of controlvoltage pulses: (1) (G₁, G_(m)), (2) (G_(m+1), G_(2m)), (3) (G_(2m+1),G_(3m)); and these three sets control voltage pulses (1, 2, 3) areprovided to the gate of the said transistors through the correspondingfirst, or second, and third input control lines; when activated by thesaid three sets of synchronous control signals (1, 2, 3) the saidcircuit feeds the said data signal to the said driving voltage outputline; and the driving voltage pulse V_(LC) generated through the controlof the gate can be used to drive the pixels to simultaneously generatethree synchronous scanning lines separated by m scanning lines on thedisplay screen, so as to display images.
 22. A method used forsimulating CRT impulse type image display, comprising the followingsteps: (1) providing a circuit comprising: a first input control line, asecond input control line, a third input control line, a first inputdata line, a first transistor, a first capacitor, a second capacitor,and a driving voltage output line; (2) providing the data signal withperiodic pulse waveform to the source of the said first transistor; (3)providing the OE and STH control signals to the first, second, and thirdoutput enable (OE) input lines and start pulse horizontal (STH) inputlines of the said gate driver, and (4) receiving the related signals viathe said input lines, the said output enable (OE) signals input by thesaid gate drivers are so controlled that the three sets of synchronouscontrol voltage pulses generated at the output of the said gate driversare selected from the following three sets of control voltage pulses:(1) (G₁, G_(m)), (2) (G_(m+1), G_(2m)), (3) (G_(2m+1), G_(3m)); andthese three sets of control voltage pulses (1, 2, 3) are provided to thegate of the said transistors through the corresponding first, second andthird input control lines, characterized in that when activated by thesaid three sets of synchronous control signals (1, 2, 3), the saidcircuit feeds the said data signal to the said driving voltage outputline; and outputting the said output driving voltage generated by theabove steps to the said pixels, so as to simultaneously generate threesynchronous scanning lines separated by m scanning lines on the displayscreen in a cyclic alternating manner, so as to display images.
 23. Themethod as claimed in claim 22, wherein since AC voltage is used as thecontrol voltage and driving voltage, these voltages indicate thephenomenon of alternating positive and negative phases during theircontrol and driving processes, and their waveforms proceed sequentiallyand periodically from time points A1 to A6 repeatedly in the followingmanner: (a) the value of driving voltage pulse D₁ in the (N−1)th framebefore time point A1 is V_(1′), and the value of the driving voltagepulse V_(LC) is V_(1′) of negative polarity; (b) at time point A1, thewaveform enters the Nth frame, at this time the value of the drivingvoltage pulse D₁ increases to V2, and due to the activation of thecontrol voltage G₁, therefore the value of output driving voltage pulseV_(LC) generated by the simulation device also increases to V₂ ofpositive polarity and it remains so until time point A2; (c) then thetime proceeds to time point A2, at this time the value of drivingvoltage pulse D₁ is V₁, and due to the activation of control voltagepulse G₁, resulting in the value of driving voltage pulse V_(LC) to dropmomentarily from V₂ to V₁ and is still of positive polarity, and thisvalue is maintained until time point A3; (d) then the time proceeds totime point A3 and enters the (N+1)th frame, at this time the value ofthe driving voltage pulse D₁ drops to V_(3′), and due to the activationof control voltage pulse G₁, the value of the driving voltage pulseV_(LC) also momentarily drops to V_(3′) of negative polarity, and itremains so until time point A4; (e) then time proceeds to A4, at thistime, the value of driving voltage pulse D₁ is still V_(1′), and due tothe activation of control voltage pulse G₁, resulting in the value ofthe driving voltage pulse V_(LC) also increases to V_(1′) and is stillof negative polarity until time point A5; and (f) then time proceeds totime point A5 and starts to enter the (N+2)th frame, at this time thevalue of the driving voltage pulse D₁ increases to V₃, and due to theactivation of the control voltage pulse G₁, resulting in the value ofthe driving voltage pulse V_(LC) also increases momentarily to V₃ ofpositive polarity, and it remains so until time point A6.
 24. The methodas claimed in claim 23, wherein when the output driving voltage V_(LC)of the simulation device between each time point is code 0, this meansthat the black line scanning is performed on the display screen duringthis period, and it can achieve the better results than inserting blackframes or shutting off the backlights, so as to optimally realize thepurpose of simulating CRT display impulse type image display with LCDdisplay.